timing verification meaning in English
定时检验
时序校验
时序验证
Examples
- One timing verification approach with the aid of the timing check system
一种借助时序检测系统进行时序验证的方法 - Design principle , structures and verilog implementations of modules in enhancement jpeg baseline mode encoder are described in detail in follow sections . each section closed with the test results of respective module in timing verification
Jpeg基本模式硬件编码器改进结构的设计思想、设计结构和verilog设计实现在其后章节中进行了详细阐述，并分别给出了改进结构中各个模块的单独测试结果。 - As the rapid development of the soc and significant increase of the electronic system complexity , the requirement of real time verification at the design stage is becoming increasing crucial , however , the price of building verification platform for specific system is not only high cost but also long development cycle
随着电子系统复杂度的增加和片上系统的发展,对系统在设计阶段进行实时验证的要求越来越重要,搭建专用模拟验证系统不仅成本高,而且周期长。 - This is one kind project of hardware multiplexer based on the high - performance system on a programmable chip ( sopc ) . in the project author integrate with the software and the hardware on a field programmable gate array ( fpga ) , not only simplifying the overall system design , moreover realizing stably , high speed , low cost multiplexer ’ s design . the dissertation carry on three verification step that include function verification 、 time verification and prototype verification to guarantee each ip can work normally to satisfy the system performance requirement . then author introduce the realization of the multiplexer in detail , as well as the test and the debugging questions met in practice and solution of the questions
本方案是一种基于可编程片上系统( sopc )的硬件复用器设计方案,其特点是将系统的软件和硬件集成在一款现场可编程门阵列( fpga )上,使用该方案不但简化了整个系统,而且实现了稳定、高速、低成本的复用器设计。对系统中各个功能模块的整合和验证采用功能仿真、时序仿真、原型验证三个步骤进行,保证系统中各个功能模块可以正常工作,并满足系统的性能要求。然后详细介绍了复用器的实现,以及测试和调试中遇到的问题及解决方法。 - This design for mvbc system adopts top - down eda common design flow . circuit design adopts veriloghdl coding description . function simulation and timing verification adopt simulation tool vcs of synopsys inc , the logic synthesis tool and fpga programming tool adopt the quartus ii of altera inc , and the fpga advice stratix ii ep2s15
该mvbc系统设计采用业界通用的自上而下的eda设计方法,电路逻辑实现采用veriloghdl硬件语言描述,功能和时序验证的动态仿真采用synopsys公司的vcs ,而逻辑综合与fpga实现采用altera公司的集成开发环境quartusii软件以及stratixiiep2s15的fpga器件。